SY100EL32VZG, DIVIDER BY 2 PECL, 100EL32, SOIC8
The SY100EL32VZG is an Integrated ÷2 Divider with differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL32V only, the VBB output has limited current sink and source capability. The reset pin is asynchronous and is asserted on the rising edge. Upon power-on, the internal flip-flop will attain a random state, the reset allows for the synchronization of multiple EL32Vs in a system.
• 510ps Propagation delay
• 3GHz Toggle frequency
• High bandwidth output transitions
• Internal 75kR input pull-down resistors
Полупроводники - Микросхемы\Логические\Счетчики