74HC4017D, Decade Counter, HC Family, 83 MHz, 2 V to 6 V, SOIC-16
|120 руб.||×||=||120 руб.|
The 74HC4017D is a 5-stage Johnson Decade Counter with 10 decoded outputs (Q0 to Q9), an output from the most significant flip-flop (Q5\-9), two clock inputs (CP0 and CP1\) and an overriding asynchronous master reset input (MR). The counter is advanced by either a low-to-high transition at CP0 while CP1\ is low or a high-to-low transition at CP1\ while CP0 is high. When cascading counters, the Q5\-9 output, which is low while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A high on MR resets the counter to zero (Q0 = Q5\-9 = high, Q1 to Q9 = low) independent of the clock inputs (CP0 and CP1\). Automatic code correction of the counter is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
• CMOS Input level
• Complies with JEDEC standard No. 7A
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