CD4018BE, Divide-By-N Counter Counter, 8.5 MHz, 3 V to 18 V, DIP-16
The CD4018BE is a CMOS Pre-settable divide-by-N Counter consists of 5 Johnson-counter stages, buffered Q outputs from each stage and counter pre-set control gating. CLOCK, RESET, DATA, PRESET ENABLE and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4 or 2 counter configurations can be implemented by feeding the Q\5, Q\4, Q\3, Q\2, Q\1 signals respectively, back to the DATA input. Divide-by functions greater than 10 can be achieved by use of multiple CD4018B units. The counter is advanced one count at the positive clock-signal transition. Schmitt Trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clears the counter to an all-zero condition. A high PRESET-ENABLE signal allows information on the JAM inputs to pre-set the counter. Anti-lock gating is provided to assure the proper counting sequence.
• Fully static operation
• 100% Tested for quiescent current at 20V
• Standardized, symmetrical output characteristics
• Meets all requirements of JEDEC tentative standard #13B
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