HEF4060BP.652, Программируемый делитель частоты [PDIP-16]
The HEF4060BP is a 14-stage ripple-carry Binary Counter/Divider and Oscillator with three oscillator terminals (RS, REXT and CEXT), ten buffered outputs and an overriding asynchronous master reset input (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. The clock inputs Schmitt-trigger action makes it highly tolerant to slower clock rise and fall times. The counter advances on the negative-going transition of RS. A high level on MR resets the counter, independent of other input conditions.
• Tolerant of slow clock rise and fall time
• Standardized symmetrical output characteristics
• Inputs and outputs are protected against electrostatic effects
• Complies with JEDEC standard JESD 13-B