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MT48LC4M32B2P-6A, SDRAM, 128MBIT, 166MHZ, 86TSOP

PartNumber: MT48LC4M32B2P-6A
Ном. номер: 8070008150
Производитель: Micron
MT48LC4M32B2P-6A, SDRAM, 128MBIT, 166MHZ, 86TSOP
Доступно на заказ 779 шт. Отгрузка со склада в г.Москва 2-3 недели.
1 190 × = 1 190
от 10 шт. — 1 010 руб.
от 100 шт. — 563 руб.


The MT48LC4M32B2P-6A is a SDR SDRAM with high-speed CMOS and uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed and random-access operation. This is a high-speed CMOS, dynamic random-access memory containing 134217728-bits. It is internally configured as a quad-bank DRAM with a synchronous interface. Read and write accesses to the SDRAM is burst-oriented, accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an active command, which is then followed by a read or write command.

• PC100-compliant
• Fully synchronous, all signals registered on positive edge of system clock
• Internal banks for hiding row access/precharge
• Auto precharge, includes concurrent auto precharge and auto refresh modes
• Self refresh mode
• LVTTL-compatible inputs and outputs

Полупроводники - Микросхемы\Память\DRAM

Технические параметры

Тип памяти
DRAM - Синхронная
Минимальная Рабочая Температура
Максимальная Рабочая Температура
Количество Выводов
Уровень Чувствительности к Влажности (MSL)
MSL 3 - 168 часов
Время Доступа
Конфигурация памяти DRAM
4М x 32бит
Стиль Корпуса Микросхемы Памяти

Дополнительная информация

Datasheet MT48LC4M32B2P-6A