SN74ABT573APW, Защелка, Прозрачная, С Тремя Состояниями, 3.2 нс, 64 мА, TSSOP, 20 вывод(-ов)
|100 руб.||×||=||100 руб.|
The SN74ABT573APW is an octal transparent D Latch with 3-state outputs. It is designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. While the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pull-up components. OE\ does not affect the internal operations of the latches.
• Ioff Supports partial-power-down mode operation
• Latch-up performance exceeds 500mA per JEDEC standard JESD 17
Полупроводники - Микросхемы\Логические\Триггеры-защелки