SN74HC165N, 8-битный сдвиговый регистр с параллельным входом, последовательным выходом [PDIP16]

The SN74HC165N is a 8-bit parallel-load Shift Register that, when clocked shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. This device also features a clock-inhibit (CLK INH) function and a complementary serial (QH) output. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register is enabled independently of the levels of the CLK, CLK INH or serial (SER) inputs.

• Outputs can drive up to 10 LSTTL loads
• Complementary outputs
• Direct overriding load (data) inputs
• Gated clock inputs
• Parallel-to-serial data conversion
• Green product and no Sb/Br