SN74LV541APW, Буфер / драйвер линии, неинвертирующий, 3 состояния, 2В до 5.5В, TSSOP-20

PartNumber: SN74LV541APW
Ном. номер: 8094564268
Производитель: Texas Instruments
SN74LV541APW, Буфер / драйвер линии, неинвертирующий, 3 состояния, 2В до 5.5В, TSSOP-20
Доступно на заказ 529 шт. Отгрузка со склада в г.Москва 2-3 недели.
74 руб. × = 74 руб.
от 10 шт. — 60 руб.
от 25 шт. — 55 руб.


The SN74LV541APW is an octal Buffer/Driver with 3-state outputs and is designed for 2 to 5.5V VCC operation. This device is ideal for driving bus lines or buffer memory address registers. It features inputs and outputs to facilitate printed circuit board layout. The 3-state control gate is a two-input AND gate with active-low inputs so that if either output-enable input is high, all corresponding outputs are in the high-impedance state. The outputs provide non-inverted data when they are not in the high-impedance state. To ensure the high-impedance state during power up or power down, both OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver The SN74LV541A device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the devices when it is powered down.

• Support mixed-mode voltage operation on all ports
• IOFF Supports partial-power-down mode operation
• Latch-up performance exceeds 250mA per JESD 17
• 6ns at 5V Propagation delay (tpd)
• <0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)
• >2.3V at VCC = 3.3V, TA = 25°C VOHV (output VOH undershoot)
• Green product and no Sb/Br

Полупроводники - Микросхемы\Логические\Буферы, Приемопередатчики и Линейные Драйверы

Технические параметры

Минимальная Рабочая Температура
Максимальная Рабочая Температура
Максимальное Напряжение Питания
Минимальное Напряжение Питания
Количество Выводов
Уровень Чувствительности к Влажности (MSL)
MSL 1 - Безлимитный
Тип Логического Устройства
Буфер, Неинвертирующий
Стиль Корпуса Микросхемы Логики