SN74LVC16244ADGVR, Буфер / драйвер линии, неинвертирующий, 1.65В до 3.6В, TVSOP-48

PartNumber: SN74LVC16244ADGVR
Ном. номер: 8036198533
Производитель: Texas Instruments
SN74LVC16244ADGVR, Буфер / драйвер линии, неинвертирующий, 1.65В до 3.6В, TVSOP-48
Доступно на заказ 1131 шт. Отгрузка со склада в г.Москва 2-3 недели.
120 руб. × = 120 руб.
от 10 шт. — 88 руб.
от 100 шт. — 65 руб.


The SN74LVC16244ADGVR is a 16-bit Buffer/Driver with 3-state outputs. This device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers and bus-oriented receivers and transmitters. It can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device provides true outputs and symmetrical active-low output-enable (OE) inputs. Inputs can be driven from either 3.3/5V devices. This feature allows the use of this device as a translator in a mixed 3.3 and 5V system environment. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver.

• IOFF Supports partial-power-down mode operation
• Supports mixed-mode signal operation on all ports
• Latch-up performance exceeds 250mA per JESD 17
• Inputs accept voltages to 5.5V
• 4.1ns at 3.3V Propagation delay (tpd)
• <0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)
• >2V at VCC = 3.3V, TA = 25°C VOHV (output VOH undershoot)
• Green product and no Sb/Br

Полупроводники - Микросхемы\Логические\Буферы, Приемопередатчики и Линейные Драйверы

Технические параметры

Минимальная Рабочая Температура
Максимальная Рабочая Температура
Максимальное Напряжение Питания
Минимальное Напряжение Питания
Количество Выводов
Уровень Чувствительности к Влажности (MSL)
MSL 1 - Безлимитный
Разрезная Лента
Тип Логического Устройства
Буфер / Драйвер Линии, Неинвертирующий
Стиль Корпуса Микросхемы Логики