MT53E256M32D2DS-053 WT:B, DRAM Chip Mobile LPDDR4 SDRAM 8Gbit 256Mx32 1.1V 200-Pin WFBGA Tray

• 1.10V VDD2/0.60V or 1.10V VDDQ operating voltage range, 256 Meg x 32 configuration
• LPDDR4, 2 die count, 535ps, tCK RL = 32/36 cycle time
• 8Gb total density, 3733Mb/s data rate per pin
• 16n prefetch DDR architecture, 8 internal banks per channel for concurrent operation
• Single-data-rate CMD/ADR entry, bidirectional/differential data strobe per byte lane
• Programmable READ and WRITE latencies, programmable and on-the-fly burst lengths
• On-chip temperature sensor to control self refresh rate
• Partial-array self refresh, selectable output drive strength, clock-stop capability
• Directed per-bank refresh for concurrent bank operation and ease of command scheduling
• 200-ball WFBGA package, operating temperature range from -30°C to +85°C