EPM240F100I5N, CPLD MAX® II Family 192 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100-Pin FBGA Tray
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см. техническую документацию
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Описание
Programmable Devices\Programmable Logic Devices\Complex Programmable Logic Devices - CPLDs
CPLD MAX® II Family 192 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100-Pin FBGA Tray
Технические параметры
| Automotive | No |
| Data Gate | No |
| ECCN (US) | EAR99 |
| EU RoHS | Compliant |
| Family Name | MAX® II |
| I/O Voltage (V) | 1.8|3.3|1.5|2.5 |
| Individual Output Enable Control | Yes |
| In-System Programmability | Yes |
| Lead Shape | Ball |
| Logic Elements | 240 |
| Maximum Clock to Output Delay (ns) | 6.9 |
| Maximum Internal Frequency (MHz) | 201.1 |
| Maximum Number of User I/Os | 80 |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Maximum Operating Temperature (°C) | 100 |
| Maximum Propagation Delay Time (ns) | 7.5|5.9 |
| Memory Size (Kbit) | 8 |
| Minimum Operating Supply Voltage (V) | 2.375 |
| Minimum Operating Temperature (°C) | -40 |
| Mounting | Surface Mount |
| Number of Global Clocks | 4 |
| Number of I/O Banks | 2 |
| Number of Inter Dielectric Layers | 6 |
| Number of Logic Blocks/Elements | 24 |
| Number of Macro Cells | 192 |
| Packaging | Tray |
| Part Status | Active |
| PCB changed | 100 |
| Pin Count | 100 |
| PPAP | No |
| Process Technology | 0.18um |
| Program Memory Type | Flash |
| Programmability | Yes |
| Reprogrammability Support | No |
| Speed Grade | 5 |
| Standard Package Name | BGA |
| Supplier Package | FBGA |
| Supplier Temperature Grade | Industrial |
| Tolerant Configuration Interface Voltage (V) | 3.3|2.5|5|1.8 |
| Tradename | MAX |
| Typical Operating Supply Voltage (V) | 3.3|2.5 |
Техническая документация
Datasheet
pdf, 8886 КБ
Дополнительная информация
Калькуляторы группы «Микросхемы программируемой логики»
Типы корпусов импортных микросхем
