AS4C256M16MD4-062BAN, DRAM LPDDR4, 4G, 256M x 16, 1.1V, 200 BALL TFBGA, 1600MHZ, ECC, AUTO TEMP - Tray

2GB/4GB/8GB/16GB/32GB LPDDR4 SDRAM Alliance Memory 2GB/4GB/8GB/16GB/32GB LPDDR4 SDRAM is organized as 1 or 2 channels per device, and the individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is a 16n prefetch architecture with an interface. It's designed to transfer two data words per clock cycle at the I/O pins. These devices offer fully synchronous operations referenced to the rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth.